Ray Shao
Systems Engineer & NTU CE Undergrad
Ray Shao is a Computer Engineering undergraduate at NTU, graduating May 2027. He spent nine months at AMD building ETL pipelines and AI tooling for the datacenter accelerator division, and is heading to Google Singapore this summer.
Outside coursework, he runs a Proxmox-based homelab for LLM inference, designed a pipelined RISC processor in Verilog, and founded the NTU Semiconductor Club, now 400+ members strong.
Projects
- Proxmox AI Datacenter — Home lab running on Proxmox — LXC containers and VMs for LLM inference, monitoring, and general compute.
- Chrome AI Privacy Extension — Chrome extension using the Prompt API and Gemini Nano for on-device text classification. Runs entirely in the browser with no server-side inference.
- uP16 · 5-Stage RISC CPU — 5-stage pipelined 16-bit RISC CPU written in Verilog and synthesized on an Artix-7 FPGA. Register file and program counter readable live on hardware via Vivado.
- Portfolio Website — This site. LCARS terminal aesthetic from Star Trek Picard, built with React 18 and Vite, deployed to GitHub Pages.
- GPU Performance Prediction — Ensemble models predicting GPU FP32 performance from hardware specs. Scraped 497 AMD and Nvidia chips from TechPowerUp (2006–2024), compared Random Forest, XGBoost, and Gradient Boosting. XGBoost on log-transformed features achieved R² 0.984 on the test set.
- Payhere · P2P Payments — P2P payment PWA built at SUTD What The Hack. Voice-activated payee selection using NLP, geospatial queries in DynamoDB, AWS Lambda and Stripe on the backend.
- VLASH-Forge — Distributed fine-tuning framework for VLA robot policies built on HuggingFace LeRobot. Fine-tune π₀.₅ on custom tasks from 12 GB VRAM and deploy to a Jetson AGX Orin at 30 Hz with a single command.
- DA3 Underwater — LoRA Depth Estimation for AUV — LoRA fine-tuning of Depth Anything 3 for underwater metric depth estimation, integrated into a ROS 2 AUV localisation pipeline. 59% AbsRel reduction, validated in live pool tests with the NTU Mecatron AUV team.
- VLASH-Piper — VLA Edge Deployment on Jetson AGX Orin — First known deployment of π₀.₅ on a 6-DOF Piper arm running entirely on a Jetson AGX Orin. 29.5x latency reduction and 65% task success rate from 50 kinesthetic demonstrations, using VLASH async inference with no datacenter GPU at runtime.
- Mixed-Precision MAC Unit — TSMC 180nm ASIC — Fixed/floating-point merged MAC unit through full RTL-to-GDSII on TSMC 180nm. FP16×FP16→FP32 accumulation and dual INT8 multiplication on a shared datapath, 4.6% area overhead vs a standalone FP MAC, 157 MHz critical path.
- Founding the NTU Semiconductor Club — Founded NTU's first dedicated semiconductor student club from scratch — faculty approval, industry partnerships, site visits, and lab access. Grew to 400 members.
- HDB3 Line Encoder — TSMC 180nm ASIC — HDB3 line encoder RTL-to-GDSII on TSMC 180nm. 4-bit lookahead shift register, 54 cells, 1,442 µm² cell area, timing closed at 250 MHz constraint with 0.961 ns post-PAR slack.
Engineering Log