MSN-012 · 2026 · asic, verilog, rtl, vlsi
HDB3 line encoder RTL-to-GDSII on TSMC 180nm. 4-bit lookahead shift register, 54 cells, 1,442 µm² cell area, timing closed at 250 MHz constraint with 0.961 ns post-PAR slack.
HDB3 (High-Density Bipolar 3) is the line code used in E1 (2.048 Mbps) and related PDH trunk links. It encodes a binary serial stream onto a three-level bipolar rail (positive mark, zero, negative mark), replacing any run of four consecutive zeros with a violation symbol that resets DC accumulation. The goal was to implement the encoder as a synchronous RTL module and take it through the full TSMC 180nm ASIC flow: behavioural simulation, synthesis, gate-level simulation, place-and-route, and post-PAR simulation.
The encoder uses a 4-bit lookahead window. Each incoming bit shifts through the window one position per clock, and the bit being encoded this cycle sits at the oldest position. Holding four bits at once lets the encoder see a full four-zero run before it commits the first output symbol, so there is no retroactive correction and the output latency is a fixed four clocks.
Encoding state is tracked with five small registers: the polarity of the last emitted mark, whether any mark has been emitted yet, the even/odd mark count since the last violation, the position within a substitution group, and a warm-up counter that discards the first three invalid window states. The HDB3 decision is purely combinational off those registers and the window contents.
Figure 2 — example HDB3 encoding on a binary bitstream, showing B00V and 000V substitutions and AMI mark alternation
Three simulation passes: behavioural (RTL direct), gate-level (Synopsys netlist with SDF back-annotation), and post-PAR (Innovus netlist with extracted parasitics). The test sequence is the 33-bit reference pattern, run twice (66 bits) plus eight flush clocks to drain the pipeline. All three passes produce identical P/N outputs.
Behavioural simulation in Synopsys DVE — 66-bit run, P and N rails encoding correctly against the HDB3 reference sequence
Gate-level simulation — synthesised netlist with SDF timing, waveforms match the behavioural run
Behavioral, gate-level, and post-PAR simulations all pass against the 33-bit × 2 reference sequence. No discrepancies between RTL and netlist.
Synopsys Design Compiler, TSMC 180nm standard cell library (tcb018g3d3, CCS characterisation, NCCOM corner). Clock constraint: 4 ns (250 MHz).
Post-synthesis: - 54 cells total — 40 combinational, 14 sequential - Cell area: 1,442.25 µm² - Critical path: `sr_reg[1]/Q` → `last_pol_reg/D`, 3.30 ns combinational delay - Timing slack: 0.63 ns (met)
Cadence Innovus at 70% target utilisation. Post-route timing analysis at the RC-max corner.
Cell area: 1,442 µm², 54 cells. Routed density: 69.4%. Worst negative slack (reg-to-reg): 0.961 ns — timing closed with margin. Zero DRC/DRV violations. Total power: 1.57 mW at 2.97 V (0.20 primary input toggle rate).
Cadence Innovus place-and-route view — 14 registers, combinational HDB3 logic, power rings and signal routing across six metal layers
The critical path after routing is `sr_reg[1]/Q` → `U37` → `U36` → `U33` → `U13` → `U12` → `U6` → `last_pol_reg/D`, totalling 2.91 ns of routed delay — better than the pre-layout wire-load estimate, which placed it at 3.30 ns. The gap is attributable to Innovus placement optimising the short register-to-combinational fanout paths.
Post-PAR simulation — waveforms from the Innovus netlist with extracted parasitics, identical to the behavioral and gate-level runs
- Verilog-2001 RTL (`hdb3_encoder`, single module) - Synopsys VCS behavioural and gate-level simulation - Synopsys Design Compiler synthesis - Cadence Innovus place-and-route - TSMC 180nm standard cell library (tcb018g3d3, CCS)