Status: Preprint. Not on arXiv. Affiliation: Nanyang Technological University, Singapore, with Google, India. Senior author: Anupam Chattopadhyay (NTU). My position: Co-author (3rd of 7 in the author list, as Shao Yingzhan). My contribution: Built most of the testing harness.
What the paper does
- Hardware specs use images (K-maps, circuit diagrams, state diagrams). Current multimodal models read them poorly, and there is little public data.
- The team generated synthetic image + Verilog pairs in three categories: Karnaugh maps, circuit diagrams, finite state machines. Each category has 3000 train samples and 100 test samples.
- They fine-tuned Llama 3.2 on this data. They compared it with GPT-4.1 and the untrained base model.
- They taught the model to call symbolic logic minimization (Espresso-based) and use the result. This gives designs with up to 55% less area and 47% less delay than the unoptimized reference (K-maps). FSMs: 40% less area, 40% less delay.
- Metrics: functional correctness (pass rate), plus area and delay proxy metrics.